As the operational speed of electronics devices relentlessly increases, the testing of such devices becomes even more problematic. The testing of digital circuitry often involves the transmission of a known data pattern to a device under test (DUT), the creation of a data pattern by the DUT in response, and the comparison of the data pattern created by the DUT to an expected data pattern. A tester may search for a match with a test pattern or a pattern related in a known manner to the test pattern. When we indicate that a tester is searching for a match with a test pattern, the actual search may be for the test pattern or a pattern related in a known manner to the test pattern.
Synchronous serial communications devices operating at high speed are particularly difficult to test. One approach to aligning a test pattern with the output of the communications device (the output of either the device's receive or transmit side) is to set the clocks of the tester and device out of phase relative to one another. In this way, the test pattern will “slide by” the matching pattern the tester employs and the test pattern may thereby be aligned with a matching pattern the tester employs. However, synchronous communications devices often employ clock-tracking circuitry, so that a tester would not be able to communicate with such a device while their clocks are out of phase with one another.
Notwithstanding the performance afforded by conventional digital circuit testers, a digital tester that provides for high-speed alignment of data patterns would be highly desirable.